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integrated circuit systems, inc. ics9214 0809e?11/17/06 block diagram rambus tm xdr tm clock generator the ics9214 clock generator provides the necessary clock signals to support the rambus xdr tm memory subsystem and redwood logic interface. the clock source is a reference clock that may or may not be modulated for spread spectrum. the ics9214 provides 4 differential clock pairs in a space saving 28-pin tssop package and provides an off-the-shelf high-performance interface solution. figure 1 shows the major components of the ics9214 xdr clock generator. these include the a pll, a bypass multiplexer and four differential output buffers. the outputs can be disabled by a logic low on the oe pin. an output is enabled by the combination of the oe pin being high, and 1 in its smbus output control register bit. the pll receives a reference clock, clk_int/c and outputs a clock signal at a frequency equal to the input frequency times a multiplier. table 2 shows the multipliers selectable via the smbus interface. this clock signal is then fed to the differential output buffers to drive the enabled clocks. disabled outputs are set to hi-z. the bypass mode routes the input clock, clk_int/c, directly to the differential output buffers, bypassing the pll. up to four ics9214 devices can be cascaded on the same smbus. table 3 shows the smbus addressing and control for the four devices. 400 ? 500 mhz clock source 4 open-drain differential output drives with short term jitter < 40ps spread spectrum compatible reference clock is differential or single-ended, 100 or 133 mhz smbus programmability for: - frequency multiplier - output enable - operating mode supports frequency multipliers of: 3, 4, 5, 6, 8, 9/2, 15/2 and 15/4 support systems where xdr subsystem is asynchronous to other system clocks 2.5v power supply pll bypass mux rega re gb regc re gd clk_int clk_inc smbclk oe oe oe oe oe bypass#/pll smbdat smb_a0 smb_a1 odclk_c3 odclk_t3 odclk_c2 odclk_t2 odclk_c1 odclk_t1 odclk_c0 odclk_t0 avdd2.5 1 28 vdd2.5 agnd 2 27 odclk_t0 irefy 3 26 odclk_c0 agnd 4 25 gnd clk_int 5 24 odclk_t1 clk_inc 6 23 odclk_c1 vdd2.5 7 22 vdd2.5 gnd 8 21 gnd smbclk 9 20 odclk_t2 smbdat 10 19 odclk_c2 oe 11 18 gnd smb_a0 12 17 odclk_t3 smb_a1 13 16 odclk_c3 bypass#/pll 14 15 vdd2.5 ics9214 pin configuration 28-pin 4.4mm tssop general description features
2 integrated circuit systems, inc. ics9214 0809e?11/17/06 pin descriptions pin # pin name pin type description 1 avdd2.5 pwr 2.5v analo g power p in for core pll 2 agnd pwr analo g ground p in for core pll 3irefy in this pin establishes the reference current for the differential clock pairs. this pin requires a fixed pr ecision resistor tied to ground in order to establish the a pp ro p riate current. 4 agnd pwr analo g ground p in for core pll 5 clk_int in "true" reference clock in p ut. 6 clk_inc in "com p lementar y " reference clock in p ut. 7 vdd2.5 pwr power su pp l y , nominal 2.5v 8 gnd pwr ground p in. 9smbclk inclock p in of smbus circuitr y , 5v tolerant 10 smbdat i/o data p in of smbus circuitr y , 5v tolerant 11 oe in active high input for enabling outputs. 0 = tri-state out p uts , 1= enable out p uts 12 smb_a0 in smbus address bit 0 ( lsb ) 13 smb_a1 in smbus address bit 1 14 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = b yp ass mode , 1= pll mode 15 vdd2.5 pwr power su pp l y , nominal 2.5v 16 odclk_c3 out "complementary" side of open drain differential clock output. this o p en drain out p ut needs an external resistor network.. 17 odclk_t3 out "true" side of open drain different ial clock output. this open drain out p ut needs an external resistor network.. 18 gnd pwr ground p in. 19 odclk_c2 out "complementary" side of open drain differential clock output. this o p en drain out p ut needs an external resistor network.. 20 odclk_t2 out "true" side of open drain different ial clock output. this open drain out p ut needs an external resistor network.. 21 gnd pwr ground p in. 22 vdd2.5 pwr power su pp l y , nominal 2.5v 23 odclk_c1 out "complementary" side of open drain differential clock output. this o p en drain out p ut needs an external resistor network.. 24 odclk_t1 out "true" side of open drain different ial clock output. this open drain out p ut needs an external resistor network.. 25 gnd pwr ground p in. 26 odclk_c0 out "complementary" side of open drain differential clock output. this o p en drain out p ut needs an external resistor network.. 27 odclk_t0 out "true" side of open drain different ial clock output. this open drain out p ut needs an external resistor network.. 28 vdd2.5 pwr power su pp l y , nominal 2.5v
3 integrated circuit systems, inc. ics9214 0809e?11/17/06 general smbus serial interface information for the ics9214 how to write: ? controller (host) sends a start bit. controller (host) sends the write address d8 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d8 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d9 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d8 (h) beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit ics (slave/receiver) controller (host) x byte ack ack data byte count = x ack slave address d9 (h) index block read operation slave address d8 (h) beginning byte = n ack ack
4 integrated circuit systems, inc. ics9214 0809e?11/17/06 smb table: output control register control function bit 7 test mode reserved for vendor rw 0 bit 6 mult2 multiplier select rw 0 bit 5 mult1 multiplier select rw 0 bit 4 mult0 multiplier select rw 1 bit 3 odclk_t/c0 output control rw 1 bit 2 odclk_t/c1 output control rw 1 bit 1 odclk_t/c2 output control rw 1 bit 0 odclk_t/c3 output control rw 1 disable = output in high-impedance state enable = output is switching smb table: frequency multiplier control register control function bit 7 reserved reserved rw 0 bit 6 reserved reserved rw 0 bit 5 reserved reserved rw 0 bit 4 reserved reserved rw 0 bit 3 reserved reserved rw 0 bit 2 reserved reserved rw 0 bit 1 reserved reserved rw 0 bit 0 test mode reserved for vendor rw 0 smb table: revision & vendor id register control function bit 7 rid4 r x bit 6 rid3 r x bit 5 rid2 r x bit 4 rid1 r x bit 3 rid0 r x bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 notes: 1. pwd = power up default disable enable -- -- -- -- -- vendor id - -- -- revision id - -- - -- 01 see table 2. pwd 1 pwd - -- byte 2 pin # name type - - byte 0 pin # name type disable enable 01 - - byte 1 pin # - 27,26 24,23 20,19 17,16 - -- name type 0 1 -- - -- - - - - -- - -- pwd disable enable disable disable enable enable disable enable
5 integrated circuit systems, inc. ics9214 0809e?11/17/06 device id and smbus device address the device id (smb_a(1:0)) is part of the smbus device address. the least significant bit of the address designates a write or read operation. table 3 shows the addresses for four ics9214 devices on the same smbus. pll multiplier table 2 shows the frequency multipliers in the pll, selectable by programming the mult0, mult1 and mult2 bits in the smbus multiplier control register. power up default is 4. table 2. pll multiplier selection bit 6 bit 5 bit 4 mult2 mult1 mult0 0003 300 3 400 0014 400 2 533 0 1 0 5 500 667 0 1 1 6 600 800 1008 800 - 3 1 0 1 9/2 450 600 1 1 0 15/2 750 - 3 1 1 1 15/4 375 500 notes 1 output frequencies are based on nominal input frequencies of 100 mhz and 133 mhz. the pll multipliers are also applicable to spread spectrum modulated input clocks. 2 default muliplier value at power up 3 outputs at these settings do not conform to the ac output characteristics, or are not supported. 4 shaded areas are under development and are not yet supported byte 0 output frequency (mhz) frequency multiplier clk_int/c = 100 mhz 1 clk_int/c = 133 mhz 1 table 3. smbus device addresses device operation smb_a1 smb_a0 wr#/rd write d8 0 read d9 1 write da 0 read db 1 write dc 0 read dd 1 write de 0 read df 1 0 2 ics9214 hex address 0 1 3 8-bit smbus device address, including oper. 1 11011 1 0 01 10
6 integrated circuit systems, inc. ics9214 0809e?11/17/06 operating modes table 4: operating modes byte 1 bit 7 bit 3 bit 2 bit 1 bit 0 l x x xxxx z z z z h x 1 xxxx h l 0 xxxx h h 0 0000 z z z z h h 0 0001 z z z clk_int/c h h 0 0010 z z clk_int/c z h h 0 0011 z z clk_int/c clk_int/c h h 0 0100 z clk_int/c zz h h 0 0101 z clk_int/c z clk_int/c h h 0 0110 z clk_int/c clk_int/c z h h 0 0111 z clk_int/c clk_int/c clk_int/c h h 0 1000 clk_int/c zzz h h 0 1001 clk_int/c zz clk_int/c h h 0 1010 clk_int/c z clk_int/c z h h 0 1011 clk_int/c z clk_int/c clk_int/c h h 0 1100 clk_int/c clk_int/c zz h h 0 1101 clk_int/c clk_int/c z clk_int/c h h 0 1110 clk_int/c clk_int/c clk_int/c z hh 0 2 1 2 1 2 1 2 1 2 clk_int/c clk_int/c clk_int/c clk_int/c notes 1 bypass mode 2 power up default mode clk_int/c 1 odclk_t/c3 odclk_t/c2 odclk_t/c1 odclk_t/c0 oe bypass#/ pll byte 0 reserved for vendor test
7 integrated circuit systems, inc. ics9214 0809e?11/17/06 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c dc characteristics - inputs ta = 0c to +70c; supply voltage avdd2.5, vdd2 .5 = 2.5 v +/- 0.125v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v dd2.5 , a vdd 2.375 2.625 v supply current i dd2.5 , i vdd 125 ma high-level input volta g e v ihclk 0.6 0.95 v low-level input volta g e v ilclk -0.15 0.15 v crossing point voltage v ixclk 0.2 0.55 v difference in crossing point voltage v ixclk 0.15 v input threshold volta g e v th 0.35 0.5 vdd2.5 v high-level input voltage for single- ended clk_in v ihse v th + 0.3 2.625 v low-level input voltage for single- ended clk_in v ilse -0.15 v th - 0.3 v high-level input volta g e v ih 1.4 2.625 v low-level input volta g e v il -0.15 0.8 v high-level input volta g e - smbus v ihsmb 1.4 3.4652 v low-level input volta g e - smbus v ilsmb -0.15 0.8 v clk_int, clk_inc singled-ended clk_in 1 oe, smb_a0, smb_a1, bypass#/pll smbclk, smbdat notes: 1 when using singled-ended clock input, vth is supplied to clk_intc as shown in figure 2. duty cycle of singled- ended clk_in is measured at v th 2 this range of smbus input high voltages allows the 9214 to co-exist with 3.3v, 2.5v and 1.8v devices on the same smbus. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in th e operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8 integrated circuit systems, inc. ics9214 0809e?11/17/06 dc characteristics - outputs ta = 0c to +70c; supply voltage avdd2.5, vdd2 .5 = 2.5 v +/- 0.125v (unless otherwise stated) parameter symbol conditions min typ max units power up latency t pu power within spec to out p uts within s p ec 3ms state transition latency 1 t co smbus or mode select transition to outputs valid and within s p ec 3ms differential output crossin g volta g e v ox measured as shown in fig. 3 0.9 1.1 v output voltage swing (peak-to-peak singled ended ) v cos measured as shown in fig. 3. excludes over and undershoot. 300 350 mv a bsolute output low voltag e volabs measured at odclk_t/c p ins 0.85 v reference voltage for swin g control current v iset v dd = 2.3v, v out = 1v 0.98 1.02 v ratio of output low current to reference current at typical v dd2.5 i ol /i ref i ref is equal to v iset /r rc . tolerance of r rc <=+/-1%. 6.8 7 7.2 - minimum current at v olabs i olabs measured at odclk_t/c pins with termination per fi g ure 3. 45 - ma low-level output voltage smbus v olsmb i ol = 4 ma -0.4v low-level output current smbus i olsmb v ol = 0.8 v 6-ma tristate output current i oz differential clock output pins - 50 ? notes: there is no output latency or glitches if a value is written to an output register. that is the same as its current contents.
9 integrated circuit systems, inc. ics9214 0809e?11/17/06 ac characteristics-inputs t a = 0c to +70c; supply voltage avdd2.5, vdd2.5 = 2.5 v +/- 0.125v (unless otherwise stated) parameter symbol condition min typ max units clk_int/clk_inc cycle time 1 t cyclein 711ns cycle-to-cycle jitter t c y c -t c y c 2 185 ps input clock duty cycle d tin over 10,000 cycles 40 60 % clk_int/clk_inc rise and fall time t r , t f 20% to 80% of input volta g e 175 700 ps difference between input rise and fall time on same pin of a sin g le device t r-f 20% to 80% of input voltage - 150 ps spread spectrum modulation fre q uenc y f inm 3 30 33 khz trian g ular modulation 0.6 % non-triangular modulation 0.54 % input clock slew rate t sl(i) 20% to 80% of input volta g e 14v/ns in p ut ca p acitance 5 c inclk clk_int, clk_inc 7 pf in p ut ca p acitance 5 c in vi = v dd2.5 or gnd 10 pf clk_int cycle time t cycletst bypass mode 4 40 ns smbus clock frequency f smb 10 100 khz notes: 4. the amount of allowed spreading for non-triangular modulation is determined by the induced downstream tracking skew. 5. capacitance measured at f = 1 mhz, dc bias = 0.9v, vac <100mv. m index 3 spread spectrum modulation index 1. measured at (vih(nom) - vil(nom))/2 and is the absolute value of the worst case deviation. 2. measured at crossin g points for differential clock input or at vth for sin g le-ended clock input 3. if input modulation is used. input modulation is not necessary.
10 integrated circuit systems, inc. ics9214 0809e?11/17/06 thermal characteristics parameter symbol conditions min. typ. max. units ja still air 120 c/w ja 1 m/s air flow 95 c/w ja 3 m/s air flow 80 c/w thermal resistance junction to case jc 20 c/w thermal resistance junction to top of case jt still air 4.5 c/w maximum case temp 120 c thermal resistance junction to ambient ac characteristics-outputs t a = 0c to +70c; supply voltage avdd2.5, vdd2.5 = 2.5 v +/- 0.125v (unless otherwise stated) parameter 1 symbol condition min typ max units output clock cycle time t cycle 1.5 2.5 ns f = 400 to 635 mhz - 40 p s f = 635 to 800 mhz - 30 p s output phase error when trackin g ssc t err,ssc -100 100 ps change in skew t skew 3 t a = 0c to +70c, avdd2.5, vdd2.5 = 2.5 v +/- 0.125v -15ps long term average output dut y c y cle dc 45 55 % f = 400 to 635 mhz - 40 p s f = 635 to 800 mhz - 30 p s output rise and fall times t r , t f 20% to 80% of output volta g e 100 300 ps difference between output rise and fall time on same pin of a single device t r-f 20% to 80% of output voltage, f = 400 to 800 mhz - 100 ps dynamic output impedance z out 4 v ol = 0.9 v 1000 - ? notes: 5. guaranteed by design and characterization, not 100% tested in production is measured at common mode voltage. 2. output short-term jitter is the absolute value fo the worst case deviation and is defined in the jitter section. 3. tskew is the timing difference between any two of the four differential clo cks and 4. zout is defined at the output pins. 1. max and min output cl ock cycle times are based on nominal output frequencies of 400 and 667 mhz respectively. for sp read spectrum modul ated input clocks, the output clo cks track the in put modulation. short term jitter (over 1 to 6 clock cycles) t j 2 t dcerr cycle-to-cycle duty cycle error
11 integrated circuit systems, inc. ics9214 0809e?11/17/06 figure 1. differential and single-ended reference clock inputs clock output drivers figure 2 shows the clock driver equivalent circuit. the differential driver produces a specified voltage swing on the channel by switching the currents going into odclk_t and odclk_c. the external resistor r rc at the irefy pin sets the maximum current. the minimum current is zero. the voltage at the irefy pin, v irefy , is by design equal to 1 v nominally, and the driver current is seven times the current flowing through r rc . so, the output low current can be estimated as i ol = 7/ r rc . the driver output characteristics are defined together with the external resistors, r 1 , r 2 , and r 3 . the output clock signals are specified at the measurement points indicated in figure 2. table 5 shows example values for the resistors. r 1 , r 2 , and r 3 and the clock driver output impedance, z out , must match the impedance of the channel, z ch , to minimize secondary reflections. z out is specified as 1000 ohms, minimum to accomplish this. the effective impedance can be estimated by: (1000r 1 /(1000+r 1 )+r2) r 3 /(1000r 1 /(1000+r 1 )+r 2 +r 3 ) pull-up resistor r t terminates the transmission line at the load to minimize clock signal reflection signal reflections. table 5 shows the resistor values for establishing and effective source termination impedance of 49.2 ohms to match a 50 ohm channel. the termination voltages are 2.5 v for v ts and 1.2 v for v t . the resistor values r1 = 38.3 ohms, r 2 = 19.1 ohms, r 3 = 54.9 ohms and r rc = 200 ohms can be used to match a 28 ohm channel. table 5. example resistor values and termination voltages for a 50 ohm channel 1 symbol parameter value tolerance unit r 1 termination resistor 39.2 +/- 1% ? r 2 termination resistor 66.5 +/- 1% ? r 3 termination resistor 93.1 +/- 1% ? r t termination resistor 49.9 +/- 1% ? r rc swing control resistor 200 +/- 1% ? v ts source termination voltage 2.5 +/-5% v v t termination voltage 1.2 +/-5% v notes: 1 a different set of resistors is used in figure 2 when testing for maximum output current of the clock driver (i olabs ). these resistors are: r 1 = 34 ? , r 2 = 31.8 ? , r 3 = 48.7 ? , r t =28 ? , r rc = 147 ? vth input inp ut xdr xdr clk_inc clk_int clk_int a. differential input b. single-ended input clock generator clock generator supply voltage
12 integrated circuit systems, inc. ics9214 0809e?11/17/06 figure 2. example system clock driver equivalent circuit figure 3. input and output voltage waveforms figure 4. crossing-point voltage input clock signal the ics9214 receives either a differential or single-ended reference clock (clk_int/c). when the reference input clock is from a differential clock source, it must meet the voltage levels and timing requirements listed in the dc characteristics ? inputs and ac characteristics ? inputs tables. for a singled-ended clock input, an external voltage divider and a supply voltage, as shown in figure 2, provide a reference voltage v th at the clk_inc pin to determine the proper switching point for clk_int. the range of v th is specified in the dc characteristics ? inputs table. r 2 r 3 r t z ch r 1 measurement differential driver point r t z ch measurement point r 2 r 3 r 1 swing current control r rc v t v t v ts v ts iset odclk_t odclk_c t f 80% v(t) 20% t r v h v l vx,nom vx+ vx- odclk_t odclk_c
13 integrated circuit systems, inc. ics9214 0809e?11/17/06 figure 7. cycle-to-cycle duty cycle error figure 6. short-term jitter figure 5. cycle-to-cycle jitter power sequencing supply voltages for the ics9214 must be applied before, or at the same time and external input and output signals. figure 8. input frequency modulation t cycle,i t j = t cycle, - t cycle, i+1 over 10,000 consecutive cycles t cycle,i+1 odclk_t odclk_c t 4cycle, i t j = t 4cycle, i - t 4cycle i+1 over 10,000 consecutive cycles t 4cycle, i+1 odclk_t odclk_c cycle (i) cycle (i+1) t pw+ (i) t cycle (i) t pw+ (i+1) t cycle (i+1) t dc,err =t pw+ (i) - t pw+ (i+1) and t pw- (i) - t pw- (i+1) t pw- (i) t pw- (i+1) odclk_t odclk_c f nom (1-p m,in )*f nom 0.5/f m,in 1/f m,in t
14 integrated circuit systems, inc. ics9214 0809e?11/17/06 sample points are for this equation are shown in table 6. phase noise data points phase noise table 6 : phase noise data points the 9214 meets the single side band phase noise spectral purity for offset frequencies between 1 mhz and 100 mhz as described by the equation: 10log[1+(50 x 106/f)2.4] -138 dbc/hz this equation is shown in figure 9. phase noise plot figure 9 : phase noise plot 1 5 10 15 20 40 80 100 -97 -114 -121 -125.2 - -133.7 -136.8 -137.3 offset frequency (mhz) ssb spectral purity (dbc/hz) 128 -150 -140 -130 -120 -110 -100 67 8 9 10 10 10 10 offs e t fre q u e ncy f , h z ssb spectral purity l(f) dbc/hz 10 log[1 + ( 50x10 6 / f ) 2.4 ] -138 ( upper lim it )
15 integrated circuit systems, inc. ics9214 0809e?11/17/06 ordering information ics9214 y g lf-t example: designation for tape and reel packaging annealed lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol
16 integrated circuit systems, inc. ics9214 0809e?11/17/06 revision history rev. issue date description page # updated smbus table byte 2, bit 3 from:0 to:1. updated pll multiplier selection table, from: byte 1 to: byte 0, and bit 2,1,0, to: bit 6,5,4. updated ordering information from "lead free" to "annealed lead free" a 4/6/2005 added phase noise spec removed unsupported speeds from pll multiplier selection, changed minimum output raise, fall times from 140ps to 100 ps compliant with rev 0.81 of xcg spec. various b 4/22/2005 1. changed write address from d2 to a valid address (d8) 2. changed read address from d3 to a valid address (d9) 3 c 11/11/2005 added the 15/4 entry in the gear table to the list of supported frequencies 5 d 4/7/2006 added thermal characteristics table. 10 e 11/17/2006 updated pin description. 2 4-5,15 3/30/2005 0.1
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a t t r i b u t e s 9 2 1 4 d g l f 9 2 1 4 d g l f t v o l t a g e 3 . 3 v ( p g g 2 8 ) ? 3 . 3 v ( p g g 2 8 ) ? p a c k a g e t s s o p 2 8 ? t s s o p 2 8 ? s p e e d n a ? n a ? t e m p e r a t u r e c ? c ? s t a t u s a c t i v e ? a c t i v e ? s a m p l e n o ? n o ? m i n i m u m o r d e r q u a n t i t y 1 ? 1 0 0 0 ? f a c t o r y o r d e r i n c r e m e n t 1 ? 1 0 0 0 ? t y p e t i t l e s i z e r e v i s i o n d a t e d a t a s h e e t ? 9 2 1 4 d a t a s h e e t 2 2 8 k b 1 1 / 1 7 / 2 0 0 6 m o d e l - i b i s ? 9 2 1 4 i b i s m o d e l 6 2 k b 0 3 / 2 3 / 2 0 0 6 r e l a t e d d o c u m e n t s h o m e ? | ? s i t e m a p ? | ? a b o u t i d t ? | ? p r e s s r o o m ? | ? i n v e s t o r r e l a t i o n s ? | ? t r a d e m a r k ? | ? p r i v a c y p o l i c y ? | ? c a r e e r s ? | ? r e g i s t e r ? | ? c o n t a c t u s ? u s e o f t h i s w e b s i t e s i g n i f i e s y o u r a g r e e m e n t t o t h e a c c e p t a b l e u s e a n d p r i v a c y p o l i c y . c o p y r i g h t 1 9 9 7 - 2 0 0 7 i n t e g r a t e d d e v i c e t e c h n o l o g y , i n c . a l l r i g h t s r e s e r v e d . n o d e : w w w . i d t . c o m

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